Among the primary objectives in the design of semiconductor memories are the reduction in the area of silicon required for the circuit and minimization of the power consumed by the circuit. One method for reducing power consumption is to "power down" portions of the memory when the overall circuit is not actively being used. Such a power down state can be initiated by a chip enable (CE) signal which is supplied in most applications for semiconductor memories.
It has further been a general design objective for semiconductor memories to pull all of the address lines to a ground state when the circuit is in a power down mode. This has been the traditional approach to assure that stored data will not be altered during the power down mode.
As a result of designing memory circuits to reduce power and to pull down all address lines there has been an increase in the number and size of transistors required to operate the circuit. This, however, increases the manufacturing costs for the circuit and can limit its operating speed. Address buffers have been a particular problem in this regard. As greater numbers of transistors are added to disable the address buffer a greater load is created for the chip enable buffer. This increase in load requires that even larger transistors be used for the chip enable buffer. Large memory circuits have a substantial number of address buffers and this multiplies the problem of increasing numbers and sizes of transistors.
In view of the problems of transistor numbers, sizes and power consumption involved in the provision of a power down mode for a semiconductor memory, there exists a need for an address buffer which can be operated in a power down mode with an absolute minimum of additional circuitry required for this function.